The present disclosure relates to a test pattern, a test method for a semiconductor device, and a computer-implemented method for designing an integrated-circuit layout, and more particularly, to a test method for a semiconductor device having a test pattern.
A semiconductor backend process includes a metal interconnect process and a via process. That is, a via is formed to connect a metal interconnect formed on a lower portion with a metal interconnect to be formed on an upper portion. Since the metal interconnect process and the via process may have various problems such as errors in design and errors in processing, metal interconnects are short-circuited or disconnected from one another, or a lower metal interconnect may be incorrectly connected with an upper metal interconnect. These failures reduce a semiconductor manufacturing yield rate and increase a manufacturing cost.